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| author | Simon South <simon@simonsouth.net> | 2023-01-08 13:31:27 -0500 |
|---|---|---|
| committer | Christopher Baines <mail@cbaines.net> | 2023-02-08 17:11:00 +0000 |
| commit | 535c61ccc31ff5910649225311f545e042b66c63 (patch) | |
| tree | 1570492ae8ceaf191856be5d15a7c4d462e074a7 /gnu | |
| parent | 3729172728a349e631178e8628313a956e16c7f1 (diff) | |
gnu: yosys: Update source and home-page URLs.
* gnu/packages/fpga.scm (yosys)[source]: Update source-repository URL.
[home-page]: Update URL.
Signed-off-by: Christopher Baines <mail@cbaines.net>
Diffstat (limited to 'gnu')
| -rw-r--r-- | gnu/packages/fpga.scm | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index a516e4dc7e..066c56401a 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -141,7 +141,7 @@ For synthesis, the compiler generates netlists in the desired format.") (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/cliffordwolf/yosys") + (url "https://github.com/YosysHQ/yosys") (commit (string-append "yosys-" version)) (recursive? #t))) ; for the ‘iverilog’ submodule (sha256 @@ -223,7 +223,7 @@ For synthesis, the compiler generates netlists in the desired format.") abc)) (propagated-inputs (list z3)) ; should be in path for yosys-smtbmc - (home-page "http://www.clifford.at/yosys/") + (home-page "https://yosyshq.net/yosys/") (synopsis "FPGA Verilog RTL synthesizer") (description "Yosys synthesizes Verilog-2005.") (license license:isc))) |